1. Field of the Invention
The present invention relates to a tester for testing a semiconductor IC circuit having multiple pins.
2. Description of the Prior Art
FIG. 2 is a block diagram of a tester for testing a semiconductor IC circuit having multiple pins, in the prior art. A timing signal generator 1 generates a test period signal, which commands to generate a test pattern. The timing signal generator 1 generates also six timing signals TS1-TS6. When a pattern address controller 2 receives the test period signals from the timing signal generator 1, the pattern address controller 2 outputs a reading-out address, which is used when a test pattern is read out.
When a pattern memory 3 receives the reading-out address from the pattern address controller 2, it outputs a test pattern having a leading address corresponding to the received reading-out address. When a formatter 4 receives the timing signals from the timing signal generator 1, it generates a test signal on the basis of the test pattern supplied from the pattern memory 3, according to the timing signals. A pin electronic circuit 5 amplifies and processes the test signal generated by the formatter 4 and outputs the test signal to an input pin of a semiconductor IC circuit. A controller 6 controls the timing of the generation of the test period signal in the timing signal generator 1, and the selection of the timing signals to be used in the formatter 4.
The function of the tester for testing a semiconductor IC circuit having multiple pins in the prior art is explained below.
A great many of test patterns are stored in the pattern memory 3 of a tester, and the timing signal generator 1 can output many sort of timing signals, so that the tester can estimate the functions of many sort of LSIs, for example, MPU or ASIC, namely the tester is assured to be a general purpose tester for testing a semiconductor IC circuit having multiple pins.
Recently, semiconductor IC circuits tend to have multiple pins, because the structure and function of ICs become more and more complex. As a result, a tester for testing such a semiconductor IC circuit must have a circuit shown in FIG. 2 in a form of a hard ware circuit for each of the input/output pins of a semiconductor IC circuit. The hard ware circuit of FIG. 2 is shown as a circuit for sending test signals to a pin 1 of a semiconductor IC circuit. Of course, a circuit having a structure same as FIG. 2 is prepared for each of the pins of a semiconductor IC circuit.
When the hardware circuit estimates a semiconductor IC circuit, at first, the timing signal generator 1 generates, under the control of the control device 6, a test period signal to send to the pattern address controller 2. The test period signal commands to generate a test pattern. At the same time, the timing signal generator 1 outputs six timing signals TS1-TS6 to the formatter 4.
The pattern address controller 2 has a counter for counting the number of receiving times of the test period signal from the timing signal generator 1. When the pattern address controller 2 receives the test period signal from the timing signal generator 1, the pattern address controller 2 is triggered to output the counted value of the counter as a reading-out address, which is used when a test pattern is read out.
When the pattern memory 3 receives the reading-out address from the pattern address controller 2, it outputs a test pattern having a leading address identical to the reading-out address. For example, when the pattern address controller 2 receives an address xe2x80x9c1000xe2x80x9d as a reading-out address, the test pattern stored at the address xe2x80x9c1000xe2x80x9d is outputted. In general, a test pattern is a signal pattern comprised of an appropriately combined xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d.
When the formatter 4 receives six timing signals TS1-TS6 from the timing signal generator 1, it selects timing signals, under the control of the control device 6, so as to generate a test signal on the basis of the test pattern sent from the pattern memory 3, according to the selected timing signals. For example, when the logical value of the test pattern is xe2x80x9c1xe2x80x9d, a test signal at HIGH level is outputted, and when the logical value of the test pattern is xe2x80x9c0xe2x80x9d, a test signal at LOW level is outputted, as shown in FIG. 3. The standing-up edge and the standing-down edge of each pulse constituting the test signal are controlled by the selected timing signals.
The pin electronic circuit 5 amplifies and processes the test signal generated by the formatter 4 and outputs the signal to an input pin of a semiconductor IC circuit.
The tester in the prior art can generate test signals having a complex wave form, using all the timing signals TS1-TS6. However, such a tester has drawbacks that it is necessary to prepare a timing signal generator, etc, for each of the input/output pins of a semiconductor IC circuit. Therefore, the size of the circuit of the tester increases according to the number of the input/output pins of a semiconductor IC circuit, hence, the price of a tester for testing a semiconductor IC circuit having multiple pins increases accordingly.
Japanese patent application JP 5-150005-A discloses a tester for testing a semiconductor IC circuit having multiple pins, in which timing signals generated by a timing signal generator are commonly used by a formatter for a pin 1 and another formatter for a pin 2. This tester has the drawback that when all the timing signals are supplied to the formatter for a pin 1, the other formatter for a pin 2 can not receive any timing signal and can not provide any test signal to the pin 2.
An object of the present invention is to eliminate these problems of the testers for testing a semiconductor IC circuit having multiple pins as in the prior art.
Another object of the present invention is to provide a tester for common use, which can be fabricated cheaply, by suppressing the augmentation of the size of the tester circuit for testing a semiconductor IC circuit having multiple pins, which may increase according to the number of the pins of a semiconductor IC circuit.
The object of the present invention is attained by a tester for testing a semiconductor IC circuit having multiple pins.
More precisely, the object is attained by a tester having a timing signal generating means, which can send timing signals to one of the test signal generating means and to more than one test signal generating means.
The timing signal generating means can be controlled to send timing signals to all of the test signal generating means or to send to at least one of the test signal generating means.
In an embodiment of the tester for testing a semiconductor IC circuit having multiple pins according to the present invention, the timing signal generating means supplies the timing signals to at least one of the test signal generating means.
In an embodiment of the tester according to the present invention, the timing signal generating means supplies the timing signal to one of the test signal generating means, and the test signal generating means generates a test signal, using all the timing signal outputted from the timing signal generating means.
In an embodiment of the tester according to the present invention, the timing signal generating means supplies the timing signals to both the test signal generating means, and the test signal generating means generate a test signal, using all the timing signal outputted from the timing signal generating means, so that identical wave form test signals are generated for two input pins of a semiconductor IC circuit.
In an embodiment of the tester according to the present invention, the timing signal generating means supplies the timing signal to both the test signal generating means, and the test signal generating means generate a test signal, using different set of the timing signals outputted from the timing signal generating means, so that different wave form test signals are generated for two input pins of a semiconductor IC circuit.
In an embodiment of the tester according to the present invention, the pattern generating means are comprised of a plurality of memories, and when the timing signal generating means output timing signals to one of the test signal generating means, the memories are used as one sequential memory, and when the timing signal generating means output timing signals to both of the test signal generating means, the memories are used as two separated memories.
In an embodiment of the tester according to the present invention, delay circuits are inserted in the timing signal transmission lines connecting the timing signal generating means and one of the test signal generating means.